The present invention relates to a system for processing the error of a bus cycle system (a bus error). By way of example, it relates to a technique which is effective when applied to a bus error process in a single-chip microcomputer that includes a CPU (central processing unit) for supporting a bus error and also another bus master module such as a DMAC (direct memory access controller).
In a single-chip microcomputer having built-in bus master modules such as a CPU and a DMAC, when a bus error has occurred in a bus cycle in which the bus master module other than the CPU starts, it can be coped with in such a way that the pertinent bus master module requests the CPU to execute an interrupt process corresponding to the bus error.
Here, the bus errors occur on such occasions that an address area in which a peripheral circuit or the like is not actually mapped has been accessed, and that the access of a user status is done to a memory area or peripheral device in which a supervisor status is set.
Heretofore, the bus error ascribable to the bus master module other than the CPU has been transacted by the process of interrupt into the CPU as described in, for example, "Signetics, SCC68070, objective specification," p. 10, published in December 1985. By way of example, when a bus error has occurred in the bus cycle of a DMAC, the DMAC ends a direct memory access operation and sets a bus error status upon the detection of the bus error. Thereafter, the DMAC releases a bus mastership and applies an interrupt signal to an interruption controller. The interruption controller gives the CPU an interrupt request for a bus error process within a range allowed according to an interrupt priority level and interrupt mask information. Thus, the CPU verifies the bus error status of the DMAC in accordance with a predetermined interrupt response cycle and runs a service program specific to the bus error process.